This invention relates to mixer circuits and, in particular, to single-sideband mixers which may be used to produce single or dual frequencies with high sideband rejection.
It is known to use xe2x80x9cmixersxe2x80x9d to mix two input signals, where one input signal has a frequency xcfx891 (i.e., 2xcfx80 f1) and the other input signal has a frequency xcfx892 (i.e., 2xcfx80 f2), to produce a first output signal having a lower frequency (i.e., the lower sideband) equal to the difference (i.e., xcfx891xe2x88x92xcfx892) of the two input signal frequencies and/or a second output signal having an upper frequency (i.e., the upper sideband) equal to the sum (i.e., xcfx891+xcfx892) of the two input signal frequencies. A single-sideband (SSB) mixer system is highly suited for generating dual-band (i.e., upper and/or lower sidebands) carrier signals for frequency translations with electronic band selection capability since it can provide either an upper or a lower sideband output by means of an electronic control.
However, it is essential for the single sideband (SSB) mixer system to have high sideband rejection in both frequency bands. That is, when the lower sideband is selected to be produced at the output of the SSB mixer system, there must be a high degree of rejection of the upper sideband and, vice versa, when the upper sideband is selected to be produced at the output of the SSB mixer system, there must be a high degree of rejection of the lower sideband.
A problem in accomplishing this result is illustrated by referring to FIG. 1 which shows a block diagram of a prior art single-frequency SSB mixer system 10. The mixer system 10 includes a first 90-degree phase shifter, 12, a second 90-degree phase shifter, 14, a first mixer, 16, a second mixer, 18, and an output combiner/summer, 20. Each one of 90-degree phase shifters 12 and 14, has two outputs. Phase shifter 12 has two xe2x80x9cquadraturexe2x80x9d outputs V11 and V12, where V11 is equal to A1cos xcfx891t and V12 is equal to B1sin(xcfx891t+xcex81); and phase shifter 14 has two xe2x80x9cquadraturexe2x80x9d outputs V21 and V22, where V21 is equal to A2cos xcfx892t and V22 is equal to B2sin(xcfx892t+xcex82).
Ideally, the two outputs of each phase shifter should have the same amplitude (i.e., A1=B1 and A2=B2) and the two outputs should be at 90 degrees (orthogonal or in quadrature) with respect to each other (i.e., xcex81=xcex82=0). However, in practice, the amplitude of the two outputs of each phase shifter may not be equal to each other (i.e., there is an amplitude imbalance) and there is a phase error, denoted by the phase angle xcex8, which is equal to the angle by which the difference between the two supposedly orthogonal outputs of a phase shifter is greater, or less, than 90 degrees. Accordingly, in the discussion to follow and in the appended claims, when reference is made to a 90xc2x0 phase shifter, without further qualification, what is meant is a phase shifter which is intended to produce two equal amplitude signals which are at 90xc2x0 to each other. However, in practice, due to various circuit limitations, the amplitude of the two output signals may not be equal (unless otherwise specified) and the phase angle between the two supposedly orthogonal output signals of a xe2x80x9c90xc2x0 phase shifterxe2x80x9d may be greater, or less, than 90xc2x0.
In the ideal case, the single frequency SSB mixer of FIG. 1 generates an output (VOUT) at the output of the combiner 20, whose frequency is solely equal to the upper sideband components (xcfx891+xcfx892). [If the outputs of the first phase shifter 12 were switched so that V11 were applied to mixer 18 and V12 to mixer 16, then the output VOUT would have a frequency which, ideally, would solely equal to the lower sideband components (1xe2x88x92xcfx892).] In practice, however, both sidebands are present at the output of the combiner 20 due to non-quadrature phase (non-zero xcex81 and xcex82) or amplitude imbalance (between A1 and B1, and between A2 and B2) introduced by phase shifters, 12 and 14.
It is known to form the phase shifters using conventional high-pass low-pass RC-CR networks of the type shown in FIG. 2A. The FIG. 2A networks yield two single-ended quadrature signals V1 and V2 These signals generally have the proper phasal relationship (i.e., 90xc2x0 ) but, the amplitudes of V1 and V2 are balanced only when xcfx89RC=1. Supplying xe2x80x9cquadraturexe2x80x9d signals to the mixers which have the correct phasal relationship (i.e., 90xc2x0 ) but which have unequal amplitude is problematic because the mixers introduce amplitude nonlinearity which makes the amplitude compensation difficult. The amplitude imbalance can be reduced by using a limiting stage to equalize the amplitude of the quadrature signals. However, these attempts normally result in excessive nonlinear limiting which, while equalizing the amplitude of the signals, causes significant phase error and the deterioration of the overall mixer system performance.
Thus, production of upper and lower sidebands with high sideband rejection is not readily achieved with single sideband mixer systems formed with high-pass low-pass 90xc2x0 phase shifters.
Applicant""s invention resides, in part, in the recognition that a single sideband mixer including two supposedly 90xc2x0 phase shifters may be used to produce upper and/or lower sidebands with a high degree of sideband rejection even when the phase shifters have a phase angle error (xcex8), so long as the phase angle error of the two phase shifters are substantially equal and the amplitude of the two orthogonal outputs of each phase shifter have substantially equal amplitudes.
Thus, in contrast to the prior art, a single sideband mixer system embodying the invention includes the application of first and second input frequencies (xcfx891, xcfx892) to first and second 90xc2x0 all-pass phase shifters to produce first and second supposedly orthogonal outputs per phase shifter. The outputs of the two phase shifters are then applied to inputs of first and second mixer circuits whose outputs are then combined to produce either the upper (the sum of xcfx891 and xcfx892) or the lower (the difference between xcfx891 and xcfx892) sidebands of the two input frequencies. The all-pass type phase shifters are used to ensure that there is little, if any, amplitude imbalance in the 90xc2x0 degree phase shifter outputs.
The first and second 90xc2x0 phase shifters embodying the invention are preferably formed such that any phase error (i.e., xcex81) in the first phase shifter is essentially equal to any phase error (i.e., xcex82) in the second phase shifter and that the phase errors xcex81 and xcex82 track each other. Accordingly, in systems embodying the invention, the first and second phase shifters are preferably formed within an integrated circuit and in close proximity to each other so that they track each other over time and varying ambient and voltage conditions. The outputs of the first and second phase shifters are supplied to mixer circuits whose outputs are combined. If the phase error of the two phase shifters track, the phase errors are significantly reduced when the mixer outputs are combined to produce an output signal VOUT.
According to one aspect of the invention, the first and second supposedly orthogonal outputs of the first 90xc2x0 phase shifter are respectively coupled via selectively enabled switching means to the inputs of the first and second mixers and the first and second supposedly orthogonal outputs of the second 90xc2x0 phase shifter are respectively fixedly coupled to the inputs of the first and second mixers. The outputs of the first and second mixers are then combined to produce either the upper sidebands or the lower sidebands of the first and second frequency input signals applied to the first and second 90xc2x0 phase shifters. For one condition of the selectively enabled switching means (e.g., the xe2x80x9cthruxe2x80x9d mode) the upper sidebands are produced and for another condition of the selectively enabled switching means (e.g., the xe2x80x9creversexe2x80x9d mode) the lower sidebands are produced.
In an integrated circuit embodying the invention, the outputs of the two mixer circuits are hard wired to each other to combine the outputs of the two mixers (e.g., the current output from one mixer is subtracted from the current output of the other mixer).